 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| Features * High Performance, Low Power AVR(R) 8-bit Microcontroller * Advanced RISC Architecture - 124 Powerful Instructions - Most Single Clock Cycle Execution - 32 x 8 General Purpose Working Registers - Fully Static Operation - Up to 1 MIPS Throughput at 1 MHz Nonvolatile Program and Data Memories - 40K Bytes of In-System Self-Programmable Flash, Endurance: 10,000 Write/Erase Cycles - Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation - 512 bytes EEPROM, Endurance: 100,000 Write/Erase Cycles - 2K Bytes Internal SRAM - Programming Lock for Software Security On-chip Debugging - Extensive On-chip Debug Support - Available through JTAG interface Battery Management Features - Two, Three, or Four Cells in Series - Deep Under-voltage Protection - Over-current Protection (Charge and Discharge) - Short-circuit Protection (Discharge) - Integrated Cell Balancing FETs - High Voltage Outputs to Drive Charge/Precharge/Discharge FETs Peripheral Features - One 8-bit Timer/Counter with Separate Prescaler, Compare Mode, and PWM - One 16-bit Timer/Counter with Separate Prescaler and Compare Mode - 12-bit Voltage ADC, Eight External and Two Internal ADC Inputs - High Resolution Coulomb Counter ADC for Current Measurements - TWI Serial Interface for SM-Bus - Programmable Wake-up Timer - Programmable Watchdog Timer Special Microcontroller Features - Power-on Reset - On-chip Voltage Regulator - External and Internal Interrupt Sources - Four Sleep Modes: Idle, Power-save, Power-down, and Power-off Packages - 48-pin LQFP Operating Voltage: 4.0 - 25V Maximum Withstand Voltage (High-voltage pins): 28V Temperature Range: -30C to 85C - Speed Grade: 1 MHz * * 8-bit Microcontroller with 40K Bytes In-System Programmable Flash ATmega406 Preliminary Summary * * * * * * * 2548ES-AVR-07/06 1. Pin Configurations Figure 1-1. Pinout ATmega406. Top View NNI NI PI PPI VREFGND VREF NV PV1 PV2 PV3 PV4 GND 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 SGND (ADC0/PCINT0) PA0 (ADC1/PCINT1) PA1 (ADC2/PCINT2) PA2 (ADC3/PCINT3) PA3 VREG VCC GND (ADC4/INT0/PCINT4) PA4 (INT1/PCINT5) PA5 (INT2/PCINT6) PA6 (INT3/PCINT7) PA7 1 2 3 4 5 6 7 8 9 10 11 12 PVT OD VFET OC OPC BATT PC0 GND PD1 PD0 (T0) PB7 (OC0B/PCINT15) PB6 (OC0A/PCINT14) 1.1 Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized. 2 ATmega406 2548ES-AVR-07/06 RESET XTAL1 XTAL2 GND (TDO/PCINT8) PB0 (TDI/PCINT9) PB1 (TMS/PCINT10) PB2 (TCK/PCINT11) PB3 (PCINT12) PB4 (PCINT13) PB5 SCL SDA ATmega406 2. Overview The ATmega406 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega406 achieves throughputs approaching 1 MIPS at 1 MHz. 2.1 Block Diagram Block Diagram PD1..0 PB7..0 Figure 2-1. XTAL1 Oscillator Circuits / Clock Generation XTAL2 Watchdog Oscillator Watchdog Timer Flash RESET Power Supervision POR & RESET SRAM 16 bit T/C1 PORTD (2) PORTB (8) OPC OC OD PPI NNI PVT PV4 PV3 PV2 PV1 NV SGND FET Control Battery Protection Wake-Up Timer JTAG 8 bit T/C0 Cell Balancing VCC Voltage ADC CPU EEPROM Voltage Reference VREF VREFGND PI NI GND BATT Charger Detect Coulumb Counter ADC DATA BUS VFET VREG Voltage Regulator TWI PORTC (1) PORTA (8) PA3..0 SCL SCA PC0 PA7..0 The ATmega406 provides the following features: a Voltage Regulator, dedicated Battery Protection Circuitry, integrated cell balancing FETs, high-voltage analog front-end, and an MCU with two ADCs with On-chip voltage reference for battery fuel gauging. The voltage regulator operates at a wide range of voltages, 4.0 - 25 volts. This voltage is regulated to a constant supply voltage of nominally 3.3 volts for the integrated logic and analog functions. The battery protection monitors the battery voltage and charge/discharge current to detect illegal conditions and protect the battery from these when required. The illegal conditions are deep under-voltage during discharging, short-circuit during discharging and over-current during charging and discharging. 3 2548ES-AVR-07/06 The integrated cell balancing FETs allow cell balancing algorithms to be implemented in software. The MCU provides the following features: 40K bytes of In-System Programmable Flash with Read-While-Write capabilities, 512 bytes EEPROM, 2K byte SRAM, 32 general purpose working registers, 18 general purpose I/O lines, 11 high-voltage I/O lines, a JTAG Interface for On-chip Debugging support and programming, two flexible Timer/Counters with PWM and compare modes, one Wake-up Timer, an SM-Bus compliant TWI module, internal and external interrupts, a 12-bit Sigma Delta ADC for voltage and temperature measurements, a high resolution Sigma Delta ADC for Coulomb Counting and instantaneous current measurements, a programmable Watchdog Timer with internal Oscillator, and four software selectable power saving modes. The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The Idle mode stops the CPU while allowing the other chip function to continue functioning. The Power-down mode allows the voltage regulator, battery protection, regulator current detection, Watchdog Timer, and Wake-up Timer to operate, while disabling all other chip functions until the next Interrupt or Hardware Reset. In Power-save mode, the Wake-up Timer and Coulomb Counter ADC continues to run. The device is manufactured using Atmel's high voltage high density non-volatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed In-System, by a conventional non-volatile memory programmer or by an On-chip Boot program running on the AVR core. The Boot program can use any interface to download the application program in the Application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash, fuel gauging ADCs, dedicated battery protection circuitry, Cell Balancing FETs, and a voltage regulator on a monolithic chip, the Atmel ATmega406 is a powerful microcontroller that provides a highly flexible and cost effective solution for Li-ion Smart Battery applications. The ATmega406 AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, and On-chip Debugger. 4 ATmega406 2548ES-AVR-07/06 ATmega406 2.2 2.2.1 Pin Descriptions VFET High voltage supply pin. This pin is used as supply for the internal voltage regulator, described in "Voltage Regulator" on page 114. In addition the voltage level on this pin is monitored by the battery protection circuit, for deep-under-voltage protection. For details, see "Battery Protection" on page 125. 2.2.2 VCC Digital supply voltage. Normally connected to VREG. 2.2.3 VREG Output from the internal Voltage Regulator. Used for external decoupling to ensure stable regulator operation. For details, see "Voltage Regulator" on page 114. 2.2.4 VREF Internal Voltage Reference for external decoupling. For details, see "Voltage Reference and Temperature Sensor" on page 121. 2.2.5 VREFGND Ground for decoupling of Internal Voltage Reference. For details, see "Voltage Reference and Temperature Sensor" on page 121. 2.2.6 GND Ground 2.2.7 SGND Signal ground pin, used as reference for Voltage-ADC conversions. For details, see "Voltage ADC - 10-channel General Purpose 12-bit Sigma-Delta ADC" on page 116. 2.2.8 Port A (PA7:PA0) PA3:PA0 serves as the analog inputs to the Voltage A/D Converter. Port A also serves as a low-voltage 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the ATmega406 as listed in "Alternate Functions of Port A" on page 68. 2.2.9 Port B (PB7:PB0) Port B is a low-voltage 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATmega406 as listed in "Alternate Functions of Port B" on page 70. 5 2548ES-AVR-07/06 2.2.10 Port C (PC0) Port C is a high voltage Open Drain output port. 2.2.11 Port D (PD1:PD0) Port D is a low-voltage 2-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATmega406 as listed in "Alternate Functions of Port D" on page 72. 2.2.12 SCL SMBUS clock, Open Drain bidirectional pin. 2.2.13 SDA SMBUS data, Open Drain bidirectional pin. 2.2.14 OC/OD/OPC High voltage output to drive external Charge/Discharge/Pre-charge FETs. For details, see "FET Control" on page 133. 2.2.15 PI/NI Unfiltered positive/negative input from external current sense resistor, used by the battery protection circuit, for over-current and short-circuit detection. For details, see "Battery Protection" on page 125. 2.2.16 PPI/NNI Filtered positive/negative input from external current sense resistor, used to by the Coulomb Counter ADC to measure charge/discharge currents flowing in the battery pack. For details, see "Coulomb Counter - Dedicated Fuel Gauging Sigma-delta ADC" on page 106. 2.2.17 NV/PV1/PV2/PV3/PV4 NV, PV1, PV2, PV3, and PV4 are the inputs for battery cells 1, 2, 3 and 4, used by the Voltage ADC to measure each cell voltage. For details, see "Voltage ADC - 10-channel General Purpose 12-bit Sigma-Delta ADC" on page 116. PVT PVT defines the pull-up level for the OD output. 2.2.18 2.2.19 BATT Input for detecting when a charger is connected. This pin also defines the pull-up level for OC and OPC outputs. 2.2.20 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 11 on page 38. Shorter pulses are not guaranteed to generate a reset. 6 ATmega406 2548ES-AVR-07/06 ATmega406 2.2.21 XTAL1 Input to the inverting Oscillator amplifier. 2.2.22 XTAL2 Output from the inverting Oscillator amplifier. 3. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 7 2548ES-AVR-07/06 4. Register Summary Address (0xFF) (0xFE) (0xFD) (0xFC) (0xFB) (0xFA) (0xF9) (0xF8) (0xF7) (0xF6) (0xF5) (0xF4) (0xF3) (0xF2) (0xF1) (0xF0) (0xEF) (0xEE) (0xED) (0xEC) (0xEB) (0xEA) (0xE9) (0xE8) (0xE7) (0xE6) (0xE5) (0xE4) (0xE3) (0xE2) (0xE1) (0xE0) (0xDF) (0xDE) (0xDD) (0xDC) (0xDB) (0xDA) (0xD9) (0xD8) (0xD7) (0xD6) (0xD5) (0xD4) (0xD3) (0xD2) (0xD1) (0xD0) (0xCF) (0xCE) (0xCD) (0xCC) (0xCB) (0xCA) (0xC9) (0xC8) (0xC7) (0xC6) (0xC5) (0xC4) (0xC3) (0xC2) (0xC1) (0xC0) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved BPPLR BPCR CBPTR BPOCD BPSCD BPDUV BPIR CBCR FCSR Reserved Reserved Reserved Reserved Reserved Reserved CADICH CADICL CADRDC CADRCC CADCSRB CADCSRA CADAC3 CADAC2 CADAC1 CADAC0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved BGCRR BGCCR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CCSR Bit 7 - - - - - - - - - Bit 6 - - - - - - - - - SCPT[3:0] DCDL[3:0] Bit 5 - - - - - - - - - Bit 4 - - - - - - - - - Bit 3 - - - - - - - - DUVD Bit 2 - - - - - - - - SCD Bit 1 - - - - - - - BPPLE DCD OCPT[3:0] CCDL[3:0] Bit 0 - - - - - - - BPPL CCD Page 128 128 129 130 130 131 - - DUVIF - - - - - - - - - - COCIF - - - - - - - - - DUVT1 DOCIF - PWMOC - - - - - - - DUVT0 SCIF - PWMOPC - - - - - - CADIC[15:8] CADIC[7:0] CADRDC[7:0] CADRCC[7:0] DUVIE CBE4 CPS - - - - - - COCIE CBE3 DFE - - - - - - SCDL[3:0] DUDL[3:0] DOCIE CBE2 CFE - - - - - - SCIE CBE1 PFD - - - - - - 132 137 134 111 111 112 112 - CADACIF CADSI1 CADRCIF CADSI0 CADICIF CADSE 110 109 111 111 111 111 - - - - - - - - - - - - - - - - - - - - - - - - - - - - BGCR2 BGCC2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - BGCR1 BGCC1 - - - - - - - - - - - - - - - XOE - - - - - - - - - - - - - - BGCR0 BGCC0 - - - - - - - - - - - - - - - ACS 29 123 123 - CADEN CADACIE - CADRCIE CADUB CADICIE CADAS1 CADAS0 CADAC[31:24] CADAC[23:16] CADAC[15:8] CADAC[7:0] - - - - - - - - - - - - - - BGCR7 BGEN - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - BGCR6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - BGCR5 BGCC5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - BGCR4 BGCC4 - - - - - - - - - - - - - - - - BGCR3 BGCC3 - - - - - - - - - - - - - - - - 8 ATmega406 2548ES-AVR-07/06 ATmega406 Address (0xBF) (0xBE) (0xBD) (0xBC) (0xBB) (0xBA) (0xB9) (0xB8) (0xB7) (0xB6) (0xB5) (0xB4) (0xB3) (0xB2) (0xB1) (0xB0) (0xAF) (0xAE) (0xAD) (0xAC) (0xAB) (0xAA) (0xA9) (0xA8) (0xA7) (0xA6) (0xA5) (0xA4) (0xA3) (0xA2) (0xA1) (0xA0) (0x9F) (0x9E) (0x9D) (0x9C) (0x9B) (0x9A) (0x99) (0x98) (0x97) (0x96) (0x95) (0x94) (0x93) (0x92) (0x91) (0x90) (0x8F) (0x8E) (0x8D) (0x8C) (0x8B) (0x8A) (0x89) (0x88) (0x87) (0x86) (0x85) (0x84) (0x83) (0x82) (0x81) (0x80) (0x7F) (0x7E) Name Reserved TWBCSR TWAMR TWCR TWDR TWAR TWSR TWBR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved OCR1AH OCR1AL Reserved Reserved TCNT1H TCNT1L Reserved Reserved TCCR1B Reserved Reserved DIDR0 Bit 7 - TWBCIF TWINT Bit 6 - TWBCIE TWEA Bit 5 - - TWSTA Bit 4 - - TWAM[6:0] TWSTO TWA[6:0] Bit 3 - - TWWC Bit 2 - TWBDT1 TWEN Bit 1 - TWBDT0 - Bit 0 - TWBCIP - TWIE TWGCE Page 169 150 147 149 149 148 147 2-wire Serial Interface Data Register TWS[7:3] 2-wire Serial Interface Bit Rate Register - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - TWPS1 TWPS0 Timer/Counter1 - Output Compare Register A High Byte Timer/Counter1 - Output Compare Register A Low Byte - - - - - - - - - - - - - - - - 101 101 Timer/Counter1 - Counter Register High Byte Timer/Counter1 - Counter Register Low Byte - - - - - - - - - - - - - - - - - - - - - - - - - - CTC1 - - VADC3D - - CS12 - - VADC2D - - CS11 - - VADC1D - - CS10 - - VADC0D 101 101 100 120 9 2548ES-AVR-07/06 Address (0x7D) (0x7C) (0x7B) (0x7A) (0x79) (0x78) (0x77) (0x76) (0x75) (0x74) (0x73) (0x72) (0x71) (0x70) (0x6F) (0x6E) (0x6D) (0x6C) (0x6B) (0x6A) (0x69) (0x68) (0x67) (0x66) (0x65) (0x64) (0x63) (0x62) (0x61) (0x60) 0x3F (0x5F) 0x3E (0x5E) 0x3D (0x5D) 0x3C (0x5C) 0x3B (0x5B) 0x3A (0x5A) 0x39 (0x59) 0x38 (0x58) 0x37 (0x57) 0x36 (0x56) 0x35 (0x55) 0x34 (0x54) 0x33 (0x53) 0x32 (0x52) 0x31 (0x51) 0x30 (0x50) 0x2F (0x4F) 0x2E (0x4E) 0x2D (0x4D) 0x2C (0x4C) 0x2B (0x4B) 0x2A (0x4A) 0x29 (0x49) 0x28 (0x48) 0x27 (0x47) 0x26 (0x46) 0x25 (0x45) 0x24 (0x44) 0x23 (0x43) 0x22 (0x42) 0x21 (0x41) 0x20 (0x40) 0x1F (0x3F) 0x1E (0x3E) 0x1D (0x3D) 0x1C (0x3C) Name Reserved VADMUX Reserved VADCSR VADCH VADCL Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved TIMSK1 TIMSK0 Reserved PCMSK1 PCMSK0 Reserved EICRA PCICR Reserved FOSCCAL Reserved PRR0 Reserved WUTCSR Reserved WDTCSR SREG SPH SPL Reserved Reserved Reserved Reserved Reserved SPMCSR Reserved MCUCR MCUSR SMCR Reserved OCDR Reserved Reserved Reserved Reserved Reserved GPIOR2 GPIOR1 Reserved OCR0B OCR0A TCNT0 TCCR0B TCCR0A GTCCR EEARH EEARL EEDR EECR GPIOR0 EIMSK EIFR Bit 7 - - - - - - - - - - - - - - - - Bit 6 - - - - - - - - - - - - - - - - Bit 5 - - - - - - - - - - - - - - - - Bit 4 - - - - - Bit 3 - VADMUX3 - VADEN Bit 2 - VADMUX2 - VADSC Bit 1 - VADMUX1 - VADCCIF Bit 0 - VADMUX0 - VADCCIE Page 118 118 119 119 VADC Data Register High byte - - - - - - - - - - - PCINT[15:8] PCINT[7:0] - - - - - - - - - OCIE0B - - - - - - - - - OCIE1A OCIE0A - - - - - - - - - TOIE1 TOIE0 - VADC Data Register Low byte - - - - - - - - - - - 102 93 59 59 - ISC31 - - - - - WUTIF - WDIF I SP15 SP7 - - - - - SPMIE - JTD - - - - - - - - - ISC30 - - - - - WUTIE - WDIE T SP14 SP6 - - - - - RWWSB - - - - - - - - - - - ISC21 - - - - - WUTCF - WDP3 H SP13 SP5 - - - - - SIGRD - - - - - - - - - - - ISC20 - - - - - WUTR - WDCE S SP12 SP4 - - - - - RWWSRE - PUD JTRF - - - - - - - - ISC11 - - - PRTWI - WUTE - WDE V SP11 SP3 - - - - - BLBSET - - WDRF SM2 - - - - - - - ISC10 - - - PRTIM1 - WUTP2 - WDP2 N SP10 SP2 - - - - - PGWRT - - BODRF SM1 - - - - - - - ISC01 PCIE1 - - PRTIM0 - WUTP1 - WDP1 Z SP9 SP1 - - - - - PGERS - IVSEL EXTRF SM0 - - - - - - - ISC00 PCIE0 - 29 - PRVADC - WUTP0 - WDP0 C SP8 SP0 - - - - - SPMEN - IVCE PORF SE - 176 - - - - - 24 24 55/73/176 46 31 183 47 10 12 12 49 36 56 58 Fast Oscillator Calibration Register On-Chip Debug Register General Purpose I/O Register 2 General Purpose I/O Register 1 - - - - - - - - Timer/Counter0 Output Compare Register B Timer/Counter0 Output Compare Register A Timer/Counter0 (8 Bit) FOC0A COM0A1 TSM - FOC0B COM0A0 - - - COM0B1 - - - COM0B0 - - WGM02 - - - CS02 - - - CS01 WGM01 - - CS00 WGM00 PSRSYNC High Byte 92 92 92 91 88 105 19 19 19 EEPROM Address Register Low Byte EEPROM Data Register - - - - - - EEPM1 - - EEPM0 - - EERIE INT3 INTF3 EEMPE INT2 INTF2 EEPE INT1 INTF1 EERE INT0 INTF0 General Purpose I/O Register 0 19 24 57 57 10 ATmega406 2548ES-AVR-07/06 ATmega406 Address 0x1B (0x3B) 0x1A (0x3A) 0x19 (0x39) 0x18 (0x38) 0x17 (0x37) 0x16 (0x36) 0x15 (0x35) 0x14 (0x34) 0x13 (0x33) 0x12 (0x32) 0x11 (0x31) 0x10 (0x30) 0x0F (0x2F) 0x0E (0x2E) 0x0D (0x2D) 0x0C (0x2C) 0x0B (0x2B) 0x0A (0x2A) 0x09 (0x29) 0x08 (0x28) 0x07 (0x27) 0x06 (0x26) 0x05 (0x25) 0x04 (0x24) 0x03 (0x23) 0x02 (0x22) 0x01 (0x21) 0x00 (0x20) Name PCIFR Reserved Reserved Reserved Reserved TIFR1 TIFR0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PORTD DDRD PIND PORTC Reserved Reserved PORTB DDRB PINB PORTA DDRA PINA Bit 7 - - - - - - - - - - - - - - - - - - - - - - PORTB7 DDB7 PINB7 PORTA7 DDA7 PINA7 Bit 6 - - - - - - - - - - - - - - - - - - - - - - PORTB6 DDB6 PINB6 PORTA6 DDA6 PINA6 Bit 5 - - - - - - - - - - - - - - - - - - - - - - PORTB5 DDB5 PINB5 PORTA5 DDA5 PINA5 Bit 4 - - - - - - - - - - - - - - - - - - - - - - PORTB4 DDB4 PINB4 PORTA4 DDA4 PINA4 Bit 3 - - - - - - - - - - - - - - - - - - - - - - PORTB3 DDB3 PINB3 PORTB3 DDA3 PINA3 Bit 2 - - - - - - OCF0B - - - - - - - - - - - - - - - PORTB2 DDB2 PINB2 PORTA2 DDA2 PINA2 Bit 1 PCIF1 - - - - OCF1A OCF0A - - - - - - - - - PORTD1 DDD1 PIND1 - - - PORTB1 DDB1 PINB1 PORTA1 DDA1 PINA1 Bit 0 PCIF0 - - - - TOV1 TOV0 - - - - - - - - - PORTD0 DDD0 PIND0 PORTC0 - - PORTB0 DDB0 PINB0 PORTA0 DDA0 PINA0 Page 102 94 74 74 74 76 74 74 74 73 73 73 Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 4. When using the I/O specific commands IN and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O registers as data space using LD and ST instructions, $20 must be added to these addresses. The ATmega406 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from $60 - $FF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. 11 2548ES-AVR-07/06 5. Instruction Set Summary Mnemonics ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER MUL MULS MULSU FMUL FMULS FMULSU RJMP IJMP JMP RCALL ICALL CALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC Rd,Rr Rd,Rr Rd,Rr Rd,K Rr, b Rr, b P, b P, b s, k s, k k k k k k k k k k k k k k k k k k k k Operands Rd, Rr Rd, Rr Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd,K Rd,K Rd Rd Rd Rd Rd Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr k Add two Registers Description Rd Rd + Rr Operation Flags Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None Z,C Z,C Z,C Z,C Z,C Z,C None None None None None None None I None Z, N,V,C,H Z, N,V,C,H Z, N,V,C,H None None None None None None None None None None None None None None None None None None None None None None #Clocks 1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 3 3 3 4 4 4 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 ARITHMETIC AND LOGIC INSTRUCTIONS Add with Carry two Registers Add Immediate to Word Subtract two Registers Subtract Constant from Register Subtract with Carry two Registers Subtract with Carry Constant from Reg. Subtract Immediate from Word Logical AND Registers Logical AND Register and Constant Logical OR Registers Logical OR Register and Constant Exclusive OR Registers One's Complement Two's Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Decrement Test for Zero or Minus Clear Register Set Register Multiply Unsigned Multiply Signed Multiply Signed with Unsigned Fractional Multiply Unsigned Fractional Multiply Signed Fractional Multiply Signed with Unsigned Relative Jump Indirect Jump to (Z) Direct Jump Relative Subroutine Call Indirect Call to (Z) Direct Subroutine Call Subroutine Return Interrupt Return Compare, Skip if Equal Compare Compare with Carry Compare Register with Immediate Skip if Bit in Register Cleared Skip if Bit in Register is Set Skip if Bit in I/O Register Cleared Skip if Bit in I/O Register is Set Branch if Status Flag Set Branch if Status Flag Cleared Branch if Equal Branch if Not Equal Branch if Carry Set Branch if Carry Cleared Branch if Same or Higher Branch if Lower Branch if Minus Branch if Plus Branch if Greater or Equal, Signed Branch if Less Than Zero, Signed Branch if Half Carry Flag Set Branch if Half Carry Flag Cleared Branch if T Flag Set Branch if T Flag Cleared Branch if Overflow Flag is Set Branch if Overflow Flag is Cleared Rd Rd + Rr + C Rdh:Rdl Rdh:Rdl + K Rd Rd - Rr Rd Rd - K Rd Rd - Rr - C Rd Rd - K - C Rdh:Rdl Rdh:Rdl - K Rd Rd * Rr Rd Rd * K Rd Rd v Rr Rd Rd v K Rd Rd Rr Rd 0xFF - Rd Rd 0x00 - Rd Rd Rd v K Rd Rd * (0xFF - K) Rd Rd + 1 Rd Rd - 1 Rd Rd * Rd Rd Rd Rd Rd 0xFF R1:R0 Rd x Rr R1:R0 Rd x Rr R1:R0 Rd x Rr 1 R1:R0 (Rd x Rr) << 1 R1:R0 (Rd x Rr) << 1 PC PC + k + 1 PC Z PC k PC PC + k + 1 PC Z PC k PC STACK PC STACK if (Rd = Rr) PC PC + 2 or 3 Rd - Rr Rd - Rr - C Rd - K if (Rr(b)=0) PC PC + 2 or 3 if (Rr(b)=1) PC PC + 2 or 3 if (P(b)=0) PC PC + 2 or 3 if (P(b)=1) PC PC + 2 or 3 if (SREG(s) = 1) then PCPC+k + 1 if (SREG(s) = 0) then PCPC+k + 1 if (Z = 1) then PC PC + k + 1 if (Z = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (N = 1) then PC PC + k + 1 if (N = 0) then PC PC + k + 1 if (N V= 0) then PC PC + k + 1 if (N V= 1) then PC PC + k + 1 if (H = 1) then PC PC + k + 1 if (H = 0) then PC PC + k + 1 if (T = 1) then PC PC + k + 1 if (T = 0) then PC PC + k + 1 if (V = 1) then PC PC + k + 1 if (V = 0) then PC PC + k + 1 R1:R0 (Rd x Rr) << BRANCH INSTRUCTIONS 12 ATmega406 2548ES-AVR-07/06 ATmega406 5. Instruction Set Summary (Continued) Mnemonics BRIE BRID SBI CBI LSL LSR ROL ROR ASR SWAP BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH DATA TRANSFER INSTRUCTIONS MOV MOVW LDI LD LD LD LD LD LD LDD LD LD LD LDD LDS ST ST ST ST ST ST STD ST ST ST STD STS LPM LPM LPM SPM IN Rd, P Rd, Z Rd, Z+ Rd, Rr Rd, Rr Rd, K Rd, X Rd, X+ Rd, - X Rd, Y Rd, Y+ Rd, - Y Rd,Y+q Rd, Z Rd, Z+ Rd, -Z Rd, Z+q Rd, k X, Rr X+, Rr - X, Rr Y, Rr Y+, Rr - Y, Rr Y+q,Rr Z, Rr Z+, Rr -Z, Rr Z+q,Rr k, Rr Move Between Registers Copy Register Word Load Immediate Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Direct to SRAM Load Program Memory Load Program Memory Load Program Memory and Post-Inc Store Program Memory In Port Rd Rr Rd+1:Rd Rr+1:Rr Rd K Rd (X) Rd (X), X X + 1 X X - 1, Rd (X) Rd (Y) Rd (Y), Y Y + 1 Y Y - 1, Rd (Y) Rd (Y + q) Rd (Z) Rd (Z), Z Z+1 Z Z - 1, Rd (Z) Rd (Z + q) Rd (k) (X) Rr (X) Rr, X X + 1 X X - 1, (X) Rr (Y) Rr (Y) Rr, Y Y + 1 Y Y - 1, (Y) Rr (Y + q) Rr (Z) Rr (Z) Rr, Z Z + 1 Z Z - 1, (Z) Rr (Z + q) Rr (k) Rr R0 (Z) Rd (Z) Rd (Z), Z Z+1 (Z) R1:R0 Rd P None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 1 k k P,b P,b Rd Rd Rd Rd Rd Rd s s Rr, b Rd, b Operands Description Branch if Interrupt Enabled Branch if Interrupt Disabled Set Bit in I/O Register Clear Bit in I/O Register Logical Shift Left Logical Shift Right Rotate Left Through Carry Rotate Right Through Carry Arithmetic Shift Right Swap Nibbles Flag Set Flag Clear Bit Store from Register to T Bit load from T to Register Set Carry Clear Carry Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag Set Twos Complement Overflow. Clear Twos Complement Overflow Set T in SREG Clear T in SREG Set Half Carry Flag in SREG Clear Half Carry Flag in SREG Operation if ( I = 1) then PC PC + k + 1 if ( I = 0) then PC PC + k + 1 I/O(P,b) 1 I/O(P,b) 0 Rd(n+1) Rd(n), Rd(0) 0 Rd(n) Rd(n+1), Rd(7) 0 Rd(0)C,Rd(n+1) Rd(n),CRd(7) Rd(7)C,Rd(n) Rd(n+1),CRd(0) Rd(n) Rd(n+1), n=0..6 Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0) SREG(s) 1 SREG(s) 0 T Rr(b) Rd(b) T C1 C0 N1 N0 Z1 Z0 I1 I0 S1 S0 V1 V0 T1 T0 H1 H0 Flags None None None None Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V None SREG(s) SREG(s) T None C C N N Z Z I I S S V V T T H H #Clocks 1/2 1/2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 BIT AND BIT-TEST INSTRUCTIONS 13 2548ES-AVR-07/06 5. Instruction Set Summary (Continued) Mnemonics OUT PUSH POP NOP SLEEP WDR BREAK Operands P, Rr Rr Rd Out Port Push Register on Stack Description P Rr STACK Rr Rd STACK Operation Flags None None None None #Clocks 1 2 2 1 1 1 N/A Pop Register from Stack No Operation Sleep Watchdog Reset Break MCU CONTROL INSTRUCTIONS (see specific descr. for Sleep function) (see specific descr. for WDR/timer) For On-chip Debug Only None None None 14 ATmega406 2548ES-AVR-07/06 ATmega406 6. Ordering Information Speed (MHz) 1 Notes: Power Supply 4.0 - 25V Ordering Code ATmega406-1AAU(2) Package(1) 48AA Operation Range Industrial (-30C to 85C) 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. Package Type 48AA 48-lead, 7 x 7 x 1.44 mm body, 0.5 mm lead pitch, Low Profile Plastic Quad Flat Package (LQFP) 15 2548ES-AVR-07/06 7. Packaging Information 7.1 48AA PIN 1 B PIN 1 IDENTIFIER e E1 E D1 D C 0~7 A1 L COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E MIN - 0.05 1.35 8.75 6.90 8.75 6.90 0.17 0.09 0.45 NOM - - 1.40 9.00 7.00 9.00 7.00 - - - 0.50 TYP MAX 1.60 0.15 1.45 9.25 7.10 9.25 7.10 0.27 0.20 0.75 Note 2 Note 2 NOTE A2 A Notes: 1. This package conforms to JEDEC reference MS-026, Variation BBC. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.08 mm maximum. E1 B C L e 10/5/2001 2325 Orchard Parkway San Jose, CA 95131 TITLE 48AA, 48-lead, 7 x 7 mm Body Size, 1.4 mm Body Thickness, 0.5 mm Lead Pitch, Low Profile Plastic Quad Flat Package (LQFP) DRAWING NO. 48AA REV. C R 16 ATmega406 2548ES-AVR-07/06 ATmega406 8. Errata 8.1 Rev. F * Voltage-ADC Common Mode Offset * Voltage Reference Spike 1. Voltage-ADC Common Mode Offset The cell conversion will have an Offset-error depending on the Common Mode (CM) level. This means that the error of a cell is depending on the voltage of the lower cells. The CM Offset is calibrated away in Atmel production when the cells are balanced. When the cells get un-balanced the CM depending offset will reappear: a. Cell 1 defines its own CM level, and will never be affected by the CM dependent offset. b. c. The CM level for Cell 2 will change if Cell 1 voltage deviates from Cell 2 voltage. The CM level for Cell 3 will change if Cell 1 and/or Cell 2 voltage deviates from the voltage at Cell 3. The worst-case error is when Cell 1 and 2 are balanced while Cell 3 voltage deviates from the voltage at Cell 1 and 2. d. The CM level for Cell 4 will change if Cell 1, Cell 2 and/or Cell 3 deviate from the voltage at Cell 4. The worst-case error is when Cell 1, Cell 2 and Cell 3 are balanced while Cell 4 voltage deviates from the voltage at Cell 1, 2 and 3. Figure 9-1 on page 18, shows the error of Cell2, Cell3 and Cell4 with 5% and 10% unbalanced cells. 17 2548ES-AVR-07/06 Figure 8-1. CM Offset with unbalanced cells. Problem Fix/Workaround Avoid getting unbalanced cells by using the internal cell balancing FETs. 2. Voltage Reference spike The Voltage Reference, VREF, will spike each time the internal temperature sensor is enabled. The temperature sensor is enabled when the VTEMP is selected in the VADMUX register and the V-ADC is enabled by the VADEN bit. The spike will be approximately 50mV and lasts for about 5ms, and it will affect any ongoing current accumulation in the CC-ADC, as well as V-ADC conversions in the period of the spike. Figure 9-2 on page 19 illustrates the Voltage Reference spike. 18 ATmega406 2548ES-AVR-07/06 ATmega406 Figure 8-2. Voltage Reference Spike Voltage 1.1 V V~50mV VREF t ~< 5ms time VADEN VADMUX3:0 XXX VTEMP Problem workaround: To get correct temperature measurement, the VADSC bit should not be written until the spike has settled (external decoupling capacitor of 1F). 19 2548ES-AVR-07/06 8.2 Rev. E * Voltage ADC not functional below 0C * Voltage-ADC Common Mode Offset * Voltage Reference Spike 1. Voltage-ADC Failing at Low Temperatures Voltage ADC not functional below 0C. The voltage ADC has a very large error below 0C, and can not be used Problem Fix/Workaround Do not use this revision below 0 celsius. 2. Voltage-ADC Common Mode Offset The cell conversion will have an Offset-error depending on the Common Mode (CM) level. This means that the error of a cell is depending on the voltage of the lower cells. The CM Offset is calibrated away in Atmel production when the cells are balanced. When the cells get un-balanced the CM depending offset will reappear: a. Cell 1 defines its own CM level, and will never be affected by the CM dependent offset. b. c. The CM level for Cell 2 will change if Cell 1 voltage deviates from Cell 2 voltage. The CM level for Cell 3 will change if Cell 1 and/or Cell 2 voltage deviates from the voltage at Cell 3. The worst-case error is when Cell 1 and 2 are balanced while Cell 3 voltage deviates from the voltage at Cell 1 and 2. d. The CM level for Cell 4 will change if Cell 1, Cell 2 and/or Cell 3 deviate from the voltage at Cell 4. The worst-case error is when Cell 1, Cell 2 and Cell 3 are balanced while Cell 4 voltage deviates from the voltage at Cell 1, 2 and 3. Figure 9-1 on page 18, shows the error of Cell2, Cell3 and Cell4 with 5% and 10% unbalanced cells. 20 ATmega406 2548ES-AVR-07/06 ATmega406 Figure 8-3. CM Offset with unbalanced cells. Problem Fix/Workaround Avoid getting unbalanced cells by using the internal cell balancing FETs. 3. Voltage Reference Spike The Voltage Reference, VREF, will spike each time a temperature measurement is started with the Voltage-ADC. Problem Fix/Workaround An accurate temperature measurement could be obtained by doing 10 temperature conversions immediately after each other. The first 9 results would be inaccurate, but the 10th conversion will be correct. Figure 9-4 on page 22 illustrates the spike on the Voltage Reference when doing 10 temperature conversions in a row (external decoupling capacitor of 1F). 21 2548ES-AVR-07/06 Figure 8-4. Voltage Voltage Reference Spike 1.1 V V~50mV VREF t ~< 5ms time VADSC (10 VTEMP conversion in a row) VADMUX3:0 XXX VTEMP If the CC-ADC is doing current accumulation while the V-ADC is doing temperature measurement, both the Instantaneous and the Accumulated conversion results will be affected. The spike on VREF will be visible on 1 Accumulated Current (CADAC3...0) and 2 Instantaneous Current (CADIC1...0) conversion results. 8.3 Rev. D * * * * * * Voltage ADC not functional below 0C Voltage-ADC Common Mode Offset Voltage Reference Spike Voltage Regulator Start-up sequence VREF influenced by MCU state EEPROM read from application code does not work in Lock Bit Mode 3 1. Voltage-ADC Failing at Low Temperatures Voltage ADC not functional below 0C. The voltage ADC has a very large error below 0C, and can not be used Problem Fix/Workaround 1. Voltage-ADC Common Mode Offset The cell conversion will have an Offset-error depending on the Common Mode (CM) level. This means that the error of a cell is depending on the voltage of the lower cells. The CM Offset is calibrated away in Atmel production when the cells are balanced. When the cells get un-balanced the CM depending offset will reappear: 22 ATmega406 2548ES-AVR-07/06 ATmega406 a. Cell 1 defines its own CM level, and will never be affected by the CM dependent offset. b. c. The CM level for Cell 2 will change if Cell 1 voltage deviates from Cell 2 voltage. The CM level for Cell 3 will change if Cell 1 and/or Cell 2 voltage deviates from the voltage at Cell 3. The worst-case error is when Cell 1 and 2 are balanced while Cell 3 voltage deviates from the voltage at Cell 1 and 2. d. The CM level for Cell 4 will change if Cell 1, Cell 2 and/or Cell 3 deviate from the voltage at Cell 4. The worst-case error is when Cell 1, Cell 2 and Cell 3 are balanced while Cell 4 voltage deviates from the voltage at Cell 1, 2 and 3. Figure 9-1 on page 18, shows the error of Cell2, Cell3 and Cell4 with 5% and 10% unbalanced cells. Figure 8-5. CM Offset with unbalanced cells. Problem Fix/Workaround Avoid getting unbalanced cells by using the internal cell balancing FETs. 23 2548ES-AVR-07/06 3. Voltage Reference Spike The Voltage Reference, VREF, will spike each time a temperature measurement is started with the Voltage-ADC. Problem Fix/Workaround An accurate temperature measurement could be obtained by doing 10 temperature conversions immediately after each other. The first 9 results would be inaccurate, but the 10th conversion will be correct. Figure 9-6 illustrates the spike on the Voltage Reference when doing 10 temperature conversions in a row (external decoupling capacitor of 1F). Figure 8-6. Voltage Voltage Reference Spike 1.1 V V~50mV VREF t ~< 5ms time VADSC (10 VTEMP conversion in a row) VADMUX3:0 XXX VTEMP If the CC-ADC is doing current accumulation while the V-ADC is doing temperature measurement, both the Instantaneous and the Accumulated conversion results will be affected. The spike on VREF will be visible on 1 Accumulated Current (CADAC3...0) and 2 Instantaneous Current (CADIC1...0) conversion results. 24 ATmega406 2548ES-AVR-07/06 ATmega406 4. Voltage Regulator Start-up sequence When powering up ATmega406 some precautions are necessary to ensure proper start-up of the Voltage Regulator. Problem Fix/Workaround The three steps below are needed to ensure proper start-up of the voltage regulator. a. Do NOT connect a capacitor larger than 100 nF on the VFET pin. This is to ensure fast rise time on the VFET pin when a supply voltage is connected. b. During assembly, always connect Cell1 first, then Cell2 and so on until the top cell is connected to PVT. If the cell voltages are about 2 volts or larger, the Voltage Regulator will normally start up properly in Power-off mode (VREG appr. 2.8 volts). After all cells have been assembled as described in step 2, a charger source must be connected at the BATT+ terminal to initialize the chip, see Section 8.3 "Power-on Reset and Charger Connect" on page 38 in the datasheet. c. If the Voltage Regulator started up in Power-off during assembly of the cells, the chip will initialize when the charger source makes the voltage at the BATT pin exceed 7 - 8 Volts. If the Voltage Regulator did not start up properly, the charger source has one additional requirement to ensure proper start up and initialization. In this case the charger source must ensure that the voltage at the VFET pin increases quickly at least 3 Volts above the voltage at the PVT pin, and that the voltage at the BATT pin exceeds 7 - 8 Volts. This will start up and initialize the chip directly. 5. VREF influenced by MCU state The reference voltage at the VREF pin depends on the following conditions of the device: a. Charger Over-current and/or Discharge Over-current Protection active but Short-circuit inactive. This will increase VREF voltage with typical 1 mV compared to a condition were all Current Protections are disabled. b. Short-circuit Protection active. Short-circuit measurements are activated when SCD in BPCR is zero (default) and DFE in FET Control and Status Register (FCSR) is set. This will increase VREF voltage with typical 8 mV compared to a condition with shortcircuit measurements inactive. V-ADC conversion of the internal VTEMP voltage. This will increase VREF voltage with typical 15 mV compared to a condition with short-circuit measurements inactive. c. Problem Fix/Work around To ensure the highest accuracy, set the Bandgap Calibration Register (BGCC) to get 1.100 V at VREF after the chip is configured with the actual Battery Protection settings and the Discharge FET is enabled. 6. EEPROM read from application code does not work in Lock Bit Mode 3 When the Memory Lock Bits LB2 and LB1 are programmed to mode 3, EEPROM read does not work from the application code. Problem Fix/Work around Do not set Lock Bit Protection Mode 3 when the application code needs to read from EEPROM. 25 2548ES-AVR-07/06 9. Datasheet Revision History 9.1 Rev 2548E - 07/06 1. 2. 3. 4. 5 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23 24. 25. 26 27. 28. 29. Updated "Pin Configurations" on page 2. Updated "ADC Noise Reduction Mode" on page 32. Updated "Power-save Mode" on page 32. Updated "Power-down Mode" on page 33. Updated "Power-off Mode" on page 33. Updated "Power Reduction Register" on page 36. Added "Voltage ADC" on page 37 and "Coloumb Counter" on page 38. Updated "Reset Sources" on page 39. Updated "Power-on Reset and Charger Connect" on page 40. Updated "External Reset" on page 41. VCC replaced by VREG in "Brown-out Detection" on page 42. Updated "Alternate Port Functions" on page 66. Updated "Internal Clock Source" on page 103. Updated "External Clock Source" on page 103. Updated Features in "Coulomb Counter - Dedicated Fuel Gauging Sigma-delta ADC" on page 106. Updated Operation in Section 18. "Coulomb Counter - Dedicated Fuel Gauging Sigma-delta ADC" on page 106. Updated Features in "Voltage Regulator" on page 114. Updated Operation in "Voltage Regulator" on page 114. Updated Bit description in "VADCL and VADCH - The V-ADC Data Register" on page 119. Updated "Writing to Bandgap Calibration Registers" on page 122. Updated Text in "Register Description for FET Control" on page 134. Added "MCUCR - MCU Control Register" on page 176. Updated "Operating Circuit" on page 223 Updated "Electrical Characteristics" on page 225. Added "Typical Characteristics - Preliminary" on page 232. Updated "Register Summary" on page 236. Updated "Errata" on page 17. Updated Table 9-2 on page 48, Table 27-5 on page 189. Updated Figure 8-1 on page 35, Figure 9-5 on page 42, Figure 17-2 on page 104, Figure 18-2 on page 107, Figure 18-3 on page 108, Figure 19-1 on page 114, Figure 29-1 on page 223. Updated Register Adresses. 30. 26 ATmega406 2548ES-AVR-07/06 ATmega406 9.2 Rev 2548D - 06/05 1. Updated Section 9. "Errata" on page 17. 9.3 Rev 2548C - 05/05 1. Updated Section 9. "Errata" on page 17. 9.4 Rev 2548B - 04/05 1. 2. 3. 4. 5. 6. 7. Typos updated, bit "PSRASY" removed, CS12:0 renamed CS1[2:0]. Removed "BGEN" bit in BGCCR register. The bandgap voltage reference is always enabled in ATmega406 revision E. Updated Figure 2-1 on page 3, Figure 6-1 on page 25, Figure 24-9 on page 137, Figure 21-1 on page 120. Updated Table 7-2 on page 33, Table 7-3 on page 34, Table 8-1 on page 38, Table 26-5 on page 181, Figure 27-1 on page 188. Updated Section 12.3.2 "Alternate Functions of Port A" on page 66 and Section 21. "Battery Protection" on page 118 description. Updated registers "External Interrupt Flag Register - EIFR" on page 55 and "Timer/Counter Control Register B - TCCR0B" on page 89. Updated Section 17.1 "Features" on page 103 and Section 17.2 "Operation" on page 103. Updated Section 19.1 "Features" on page 111. Updated Section 20.2 "Register Description for Voltage Reference and Temperature Sensor" on page 116. Updated Section 29. "Electrical Characteristics" on page 211. Updated Section 35. "Errata" on page 225. 8. 9. 27 2548ES-AVR-07/06 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France Tel: (33) 4-76-58-30-00 Fax: (33) 4-76-58-34-80 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 ASIC/ASSP/Smart Cards Zone Industrielle 13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00 Fax: (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL'S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL'S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Atmel's products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. (c) 2006 Atmel Corporation. All rights reserved. Atmel (R), logo and combinations thereof, Everywhere You Are (R), AVR(R), and AVR Studio (R) are the trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. 2548ES-AVR-07/06 |
Price & Availability of ATMEGA40606
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |